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| INTEGRATED CIRCUITS NE56605-42 System reset with built-in watchdog timer Product data Supersedes data of 2001 Apr 24 File under Integrated Circuits, Standard Analog 2001 Aug 22 Philips Semiconductors Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 GENERAL DESCRIPTION The NE56605-42 is designed to generate a reset signal, at a threshold voltage of 4.2 V, for a variety of microprocessor and logic systems. Accurate reset signals are generated during momentary power interruptions, or whenever power supply voltages sag to intolerable levels. The NE56605-42 has a built-in Watchdog Timer to monitor the microprocessor and ensure it is operating properly. Any abnormal system operations due to microprocessor malfunctions are terminated by the watchdog's generating a system reset. The NE56605-42 has a watchdog monitoring time of 10 ms (typical). The NE56605-42 is offered in the SO8 surface mount package. FEATURES * Both positive and negative logic reset output signals are available * Accurate threshold detection * Internal power-on reset delay * Internal watchdog timer programmable with external capacitor * Watchdog monitoring time of 10 ms * Reset assertion with VCC down to 0.8 VDC (typical) * Few external components required. SIMPLIFIED SYSTEM DIAGRAM VCC 5 6 WDC APPLICATIONS * Microcomputer systems * Logic systems. R VS 7 NE56605-42 8 RESET GENERATOR 2 RESET LOGIC SYSTEM RESET RESET CLK RESET CLK GND R C VREF PROGRAMMABLE WATCHDOG TIMER 3 4 GND 1 CT SL01282 Figure 1. Simplified system diagram. ORDERING INFORMATION PACKAGE TYPE NUMBER NE56605-42D NAME SO8 DESCRIPTION plastic small outline package; 8 leads; body width 3.9 mm TEMPERATURE RANGE -20 to +70 C 2001 Aug 22 2 853-2251 26949 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 Part number marking The package is marked with a four letter code in the first line to the right of the logo. The first three letters designate the product. The fourth letter, represented by `x', is a date tracking code. The remaining two or three lines of characters are internal manufacturing codes. PIN CONFIGURATION TOP VIEW CT RESET CLK GND 7 6 1 2 8 7 RESET VS WDC VCC SO8 3 4 6 5 8 5 SL01279 Figure 2. Pin configuration. 1 2 3 Part number NE56605-42 Marking AA E x PIN DESCRIPTION PIN 1 CT SYMBOL DESCRIPTION tWDM, tWDR, tPR adjustment pin. tWDM, tWDR, tPR times are dependent on the value of external CT capacitor used. See Figure 18 (Timing Diagram) for definition of tWDM, tWDR, tPR times. Reset HIGH output pin. Clock input pin from logic system for watchdog timer. Circuit ground. Power supply pin for circuit. Watchdog timer control pin. The watchdog timer is enabled when this pin is unconnected, and disabled when this pin is connected to ground. Detection threshold adjustment pin. The detection threshold can be increased by connecting this pin to VCC with a pull-up resistor. The detection threshold can be decreased by connecting this pin to ground with a pull-down resistor. Reset LOW output pin. 2 3 4 5 6 RESET CLK GND VCC WDC 7 VS 8 RESET MAXIMUM RATINGS SYMBOL VCC VS VCLK VOH Toper Tstg P Power supply voltage VS pin voltage CLK pin voltage RESET and RESET pin voltage Operating temperature Storage temperature Power dissipation PARAMETER MIN. -0.3 -0.3 -0.3 -0.3 -20 -40 - MAX. 10 10 10 10 70 125 250 UNIT V V V V C C mW 4 2001 Aug 22 3 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 DC ELECTRICAL CHARACTERISTICS Characteristics measured with VCC = 5.0 V, and Tamb = 25 C, unless otherwise specified. See Figure 23 (Test circuit 1) for test configuration used for DC parameters. SYMBOL ICC VSL VSH VS/Tamb Vhys VTH IIH IIL VOH1 VOH2 VOL1 VOL2 VOL3 VOL4 IOL1 IOL2 ICT1 ICT2 VCCL1 VCCL2 Supply voltage to assert reset operation CT charge current Output sink current Output voltage, LOW-level PARAMETER Supply current during watchdog timer operation Reset detection threshold Reset detection threshold Temperature coefficient of reset threshold Reset threshold hysteresis CLK input threshold CLK input current, HIGH-level CLK input current, LOW-level Output voltage, HIGH-level VCLK = 5.0 V VCLK = 0 V IRESET = -5.0 A; VS = open IRESET current = -5.0 mA; VS = 0 V IRESET = 3.0 mA; VS = 0 V IRESET = 10 mA; VS = 0 V IRESET = 0.5 mA; VS = open IRESET = 1.0 mA; VS = open VRESET = 1.0 V; VS = 0 V VRESET = 1.0 V; VS = open VCT = 1.0 V; WDC = open during watchdog operation VCT = 1.0 V; during power-on reset operation VRESET = 0.4 V; RESET current = 0.2 mA VRESET = VCC - 0.1 V; 1 M resistor (pin 2 to GND) VS = open; VCC = falling VS = open; VCC = rising -20 C Tamb 70 C VHYS = VSH (rising VCC) - VSL (falling VCC) CONDITIONS MIN. - 4.05 4.15 - 50 0.8 - -20 4.5 4.5 - - - - 10 1.0 -8 -0.8 - - TYP. 0.7 4.20 4.30 0.01 100 1.2 0 -10 4.8 4.8 0.2 0.3 0.2 0.3 16 2.0 -12 -1.2 0.8 0.8 MAX. 1.0 4.35 4.45 - 150 2.0 1.0 -3.0 - - 0.4 0.5 0.4 0.5 - - -24 -2.4 1.0 1.0 UNIT mA V V %/C mV V A A V V V V V V mA mA A A V V 2001 Aug 22 4 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 AC ELECTRICAL CHARACTERISTICS Characteristics measured with VCC = 5.0 V, and Tamb = 25 C, unless otherwise specified. See Figure 24 (Test circuit 2) for test configuration used for AC parameters. SYMBOL tP1 tCLKW tCLK tWDM tWDR tPR tPD1 tPD2 tR1 tR2 tF1 tF2 RESET, RESET fall time (Note 5) PARAMETER Minimum power supply pulse width for detection Clock input pulse width Clock input cycle Watchdog monitoring time (Notes 1, 6) Watchdog reset time (Notes 2, 6) Power-on reset delay time (Notes 3, 6) RESET, RESET propagation delay time (Note 4) RESET, RESET rise time (Note 5) CT = 0.1 F; RCT = open CT = 0.1 F VCC = rising from 0 V; CT = 0.1 F RESET: RL1 = 2.2 k; CL1 = 100 pF RESET: RL2 = 10 k; CL2 = 20 pF RESET: RL1 = 2.2 k; CL1 = 100 pF RESET: RL2 = 10 k; CL2 = 20 pF RESET: RL1 = 2.2 k; CL1 = 100 pF RESET: RL2 = 10 k; CL2 = 20 pF CONDITIONS 4.0 V negative-going VCC pulse 5.0 V MIN. 8.0 3.0 20 5.0 1.0 50 - - - - - - TYP. - - - 10 2.0 100 2.0 3.0 1.0 1.0 0.1 0.5 MAX. - - - 15 3.0 150 10 10 1.5 1.5 0.5 1.0 UNIT s s s ms ms ms s s s s s s NOTES: 1. `Watchdog monitoring time' is the duration from the last pulse (negative-going edge) of the timer clear clock pulse until reset output pulse occurs (see Figure 18). A reset signal is output if a clock pulse is not input during this time. 2. `Watchdog reset time' is the reset pulse width (see Figure 18). 3. `Power-on reset delay time' is the duration measured from the time VCC exceeds the upper detection threshold (VSH) and power-on reset release is experienced (RESET output HIGH; RESET output LOW). 4. `RESET, RESET propagation delay time' is the duration from when the supply voltage sags below the lower detection threshold (VSL) and reset occurs (RESET output LOW, RESET output HIGH). 5. RESET, RESET rise and fall times are measured at 10% and 90% output levels. 6. Watchdog monitoring time (tWDM), watchdog reset time (tWDR), and power-on reset delay time (tPR) during power-on can be modified by varying the CT capacitance. The times can be approximated by applying the following formula. The recommended range for CT is 0.001 F to 10 F. Formula 1. Calculation for approximate tPR, tWDM, and tWDR values: tPR (ms) 1000 x CT (F) tWDM (ms) 100 x CT (F) tWDR (ms) 20 x CT (F) Example: When CT = 0.1 F and WDC = open: tPR 100 ms tWDM 10 ms tWDR 2.0 ms 2001 Aug 22 5 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 TYPICAL PERFORMANCE CURVES 1 .4 I CC POWER SUPPLY CURRENT (mA) Tamb = 35 C VRST, RESET OUTPUT VOLTAGE (V) 1 .2 1.0 0.8 0.6 0.4 0.2 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VCC, POWER SUPPLY VOLTAGE (V) WITH CLOCK SIGNALS TO WATCHDOG WITHOUT CLOCK SIGNALS TO WATCHDOG 5.0 Tamb = -25 C, 25 C, 75 C 4.0 6.0 RESET PULL-UP R = 10 k 3.0 2.0 VSL 1.0 VSH VOL 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VCC, POWER SUPPLY VOLTAGE (V) SL01303 SL01304 Figure 3. Power supply current versus voltage. Figure 4. RESET output voltage versus supply voltage. 6.0 5.0 VSL , V SH , DETECTION THRESHOLD (V) VRST , RESET OUTPUT VOLTAGE (V) RESET PULL-UP R = 2.2 k 4.5 VCC = RISING (VSH) VCC = FALLING (VSL) 4.4 VSH 4.3 VSL 4.2 4.0 3.0 VSL 2.0 Tamb = -25 C 1.0 Tamb = 25 C Tamb = 75 C VOL VSH 4.1 0 0 1.0 2.0 3.0 4.0 5.0 6.0 4.0 -40 -20 0 20 40 60 80 100 VCC POWER SUPPLY VOLTAGE (V) Tamb, AMBIENT TEMPERATURE (C) SL01302 SL01301 Figure 5. RESET output voltage versus supply voltage. 600 VOL , RESET OUTPUT SATURATION (mV) Figure 6. Detection threshold versus temperature. 600 VOL , RESET OUTPUT SATURATION (mV) VCC = 5.0 V RESET PULL-UP R = 2.2 k 500 VCC = 5.0 V RESET PULL-UP R = 10 k 500 400 Tamb = 75 C 400 Tamb = 75 C 300 Tamb = 25 C Tamb = -25 C 300 200 200 100 Tamb = 25 C 0 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 Tamb = -25 C 100 0 -1.4 -1.6 -1.8 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 IOL, RESET OUTPUT SINK CURRENT (mA) IOL, RESET OUTPUT SINK CURRENT (mA) SL01300 SL01299 Figure 7. RESET saturation versus sink current. Figure 8. RESET saturation versus sink current. 2001 Aug 22 6 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 5.2 VOM, RESET HIGH LEVEL OUTPUT (V) VOM, RESET HIGH LEVEL OUTPUT (V) VCC = 5.0 V Tamb = 25 C 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 VCC = 5.0 V Tamb = 25 C 5.0 4.8 4.6 4.4 4.2 4.0 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 IOM, RESET HIGH OUTPUT LEAKAGE CURRENT (A) 0 -2.0 -4.0 -6.0 -8.0 -10 -12 -14 -16 IOM, RESET HIGH OUTPUT LEAKAGE CURRENT (A) SL01298 SL01297 Figure 9. RESET HIGH-level voltage versus current. Figure 10. RESET HIGH-level voltage versus current. 140 t WDM , WATCHDOG MONITORING (ms) VCC = 5.0 V CT = 0.1 F RCT = Open 120 140 VCC = 5.0 V CT = 0.1 F RCT = Open 120 t PR , POWER-ON RESET HOLD (ms) 100 100 80 80 60 -40 -20 0 20 40 60 80 100 Tamb, AMBIENT TEMPERATURE (5C) 60 -40 -20 0 20 40 60 80 100 Tamb, AMBIENT TEMPERATURE (5C) SL01296 SL01295 Figure 11. Power-on reset hold time versus temperature. Figure 12. Watchdog monitoring time versus temperature. 3.0 VCC = 5.0 V CT = 0.1 F t WDR , WATCHDOG RESET (ms) 2.5 2.0 1.5 1.0 -40 -20 0 20 40 60 80 100 Tamb, AMBIENT TEMPERATURE (C) SL01294 Figure 13. Watchdog reset time versus temperature. 2001 Aug 22 7 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 104 t PR , POWER-ON RESET HOLD (ms) VCC = 5.0 V Tamb = 25 C 103 t WDR , WATCHDOG RESET (ms) 102 VCC = 5.0 V Tamb = 25 C 10 102 1.0 10 10-1 1.0 10-3 10-2 10-1 CT, CAPACITANCE (F) 1.0 10 10-2 10-3 10-2 10-1 CT, CAPACITANCE (F) 1.0 10 SL01290 SL01291 Figure 14. Power-on reset hold time versus CT. Figure 15. Watchdog reset time versus CT. 103 t WDM, WATCHDOG MONITORING (ms) VCC = 5.0 V Tamb = 25 C 102 10 1.0 10-1 10-3 10-2 10-1 CT, CAPACITANCE (F) 1.0 10 SL01292 Figure 16. Watchdog reset time versus CT. 2001 Aug 22 8 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 TECHNICAL DESCRIPTION General discussion The NE56605-42 combines a watchdog timer and an undervoltage reset function in a single SO8 surface mount package. This provides a space-saving solution for maintaining proper operation of typical 5.0 volt microprocessor-based logic systems. Either function, or both, can force the microprocessor into a reset. While the watchdog monitors the microprocessor operation, the undervoltage reset monitors the supply voltage to the microprocessor. If the microprocessor clock signal ceases or becomes erratic, the NE56605-42 outputs a reset signal to the microprocessor. If the microprocessor supply voltage sags to 4.2 volts or less, the NE56605-42 outputs a reset signal for the duration of the supply voltage deficiency. The undervoltage reset signal allows the microprocessor to shut down in an orderly manner to avoid system corruption. In addition to a single reset output, the NE56605-42 has complementary RESET and RESET outputs for system use. The undervoltage detection threshold incorporates hysteresis to prevent generating erratic resets. The watchdog timer requires a pulse input. Normally this signal comes from the system microprocessor's clock. For operation, an external capacitor (CT) must be connected from Pin 1 to ground. Normally a 0.1 F capacitor is used for CT. The CT capacitor and a fixed internal resistance establish the required minimum frequency of watchdog input signal for the device to not output a reset signal. In the absence of a watchdog input pulse, the CT capacitor charges to the 0.2 volt threshold of the internal comparator, causing a reset signal to be output. If microprocessor clock signals are received within the required interval, no watchdog reset signal will be output. Grounding the watchdog control pin (WDC, Pin 6) disables the watchdog function. Removing the ground from Pin 6, allowing it to float, enables the watchdog function. Enabling or disabling the watchdog function has no effect on the undervoltage detection function. Although the temperature coefficient of detection threshold is specified over a temperature of -20 C to +70 C, the device will support operation in excess of this temperature range. See the supporting curves for performance over the full temperature range of -30 C to +85 C. Some degradation in performance will be experienced at the temperature extremes and the system designer should take this into account. VCC WDC 5 CP 1.2 A 1.2 A 0.1 V R 54 k SQ 7 R C 26 k SQ R 8.2 k 3 PULSE GENERATOR 0.2 V R SQ R R R R R 47 k 12 A 6 R R 1 CT 4 GND 2 RESET 8 RESET SL01293 Figure 17. Functional diagram. 2001 Aug 22 9 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 Timing diagram The timing diagram shown in Figure 18 depicts the operation of the device. Letters indicate events on the TIME axis. A: At start-up `A', the VCC and RESET voltages begin to rise. Also the RESET voltage initially rises, but then abruptly returns to a LOW state. This is due to VCC reaching the level (approximately 0.8 V) that activates the internal bias circuitry, asserting RESET. B: Just before `B', the CT voltage starts to ramp up. This is caused by, and coincident to, VCC reaching the threshold level of VSH. At this level the device is in full operation. The RESET output continues to rise as VCC rises above VSH. This is normal. C: At `C', VCC is above the undervoltage detect threshold, and CT has ramped up to its upper detect level. At this point, the device removes the hold on the resets. RESET goes HIGH while RESET goes LOW. Also, an internal ramp discharge transistor activates, discharging CT. In a microprocessor-based system these events remove the reset from the microprocessor, allowing it to function normally. The system must send clock signals to the Watchdog Timer often enough to prevent CT from ramping up to the CT threshold, to prevent reset signals from being generated. Each clock signal discharges CT. C-D: Midway between `C' and `D', the CLK signals cease allowing the CT voltage to ramp up to its upper threshold at `D'. At this time, reset signals are generated (RESET goes LOW; RESET goes HIGH). The device attempts to come out of reset as the CT voltage is discharged and finally does come out of reset when CLK signals are re-established after two attempts of CT. E-F: Immediately before `E', falling VCC causes the RESET signal to sag. CLK signals are still being received, CT is within normal operating range, and reset signals are not output. VCC continues to sag until the VSL undervoltage threshold is reached. At that time, reset signals are generated (RESET goes LOW; RESET goes HIGH). At `E', VCC starts to rise, and the Reset voltage rises with VCC. However, CT voltage does not start to ramp up until `F' when VCC reaches the VSH upper threshold. G: The reset outputs are released at `G' when CT reaches the upper threshold level again. After `G', normal CLK signals are received, but at a lower frequency than those following event `C'. The frequency is above the minimum frequency required to keep the device from outputting reset signals. G-H: At `H', VCC is normal, CLK signals are being received, and no reset signals are output. At event `H', the VCC starts falling, causing RESET to also fall. J: At event `J', VCC sags to the point where the VSL undervoltage threshold point is reached, and at that level reset signals are output (RESET to a LOW state, and RESET to a HIGH state). As the VCC voltage falls lower, the Reset voltage falls lower. K: At event `K', the VCC voltage has deteriorated to a level where normal internal circuit bias is no longer able to maintain a RESET, and as a result may exhibit a slight rise to something less than 0.8 V. As VCC decays even further, RESET also decreases to zero. VSH VSL VCC tCLK CLK CTthresh CT tPR RESET 0.8 V tWDM tWDR RESET A B C D TIME E F G H J K SL01283 Figure 18. Timing diagram. 2001 Aug 22 10 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 Application information The detection threshold voltage can be adjusted by externally influencing the internal divider reference voltage. Figures 19 and 21 show a method to lower and raise the threshold voltage. Figures 20 and 22 show the influence of the pull-down and pull-up resistors on the threshold voltage. The use of a capacitor (1000 pF or larger) from Pin 7 to ground is recommended to filter out noise from being imposed on the threshold voltages. The Reset Detection Threshold can be decreased by connecting an external resistor R1 from Pin 7 to VCC, as shown in Figure 19. See Figure 20 to determine the approximate value of R1 to use. The Reset Detection Threshold can be increased by connecting an external resistor R2 from Pin 7 to ground, as shown in Figure 21. See Figure 22 to determine the approximate value of R2 to use. VCC R1 1 8 LOGIC SYSTEM Vs, RESET DETECTION THRESHOLD (V) 5.0 VCC = 5.0 V Tamb = 25 C CT = 0.1 F VSH 4.0 VSL RESET CLK RESET NE56605-42 2 3 4 7 6 GND 5 1000 pF 3.5 3.0 0 100 200 300 400 500 600 700 R1, EXTERNAL PIN 7 TO VCC RESISTOR (k) SL01286 SL01289 Figure 19. Circuit to lower detection threshold. Figure 20. Reset detection threshold versus external R1. VCC LOGIC SYSTEM Vs, RESET DETECTION THRESHOLD (V) 5.1 5.0 4.9 4.8 4.7 4.6 VSH 4.5 4.4 4.3 0 100 200 300 400 500 600 700 R2, EXTERNAL PIN 7 TO GROUND RESISTOR (k) VSL VCC = 5.0 V Tamb = 25 C CT = 0.1 F 1 8 RESET CLK RESET NE56605-42 2 3 4 7 6 GND 5 R2 1000 pF SL01287 SL01288 Figure 21. Circuit to raise detection threshold. Figure 22. Reset detection threshold versus external R2. 2001 Aug 22 11 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 Parametric testing DC and AC Characteristics can be tested using the circuits shown in Figures 23 and 24. Associated switch and power supply settings are shown in Table 1 and Table 2, respectively. 1000 pF S2 A ABC S1 V VO1 IO1 8 RESET S3 CT 1 CRT CRT1 VO0 VCT A B R 1.0 M IRESET IRESET A ICT RESET CLK 2 A IO2 3 A ICLK GND 4 7 VS 6 RCT 5 VCC S5 S7 A ICC 0.1 F VCC S4 C CRT V VO2 S6 CRT2 VCLK SL01284 Figure 23. Test Circuit 1 (DC parameters). Table 1. DC characteristics Test Circuit 1 switch and power supply settings Parameter Power supply current Reset threshold (LOW) (Note 1) Reset threshold (HIGH) (Note 2) Clock input threshold (Note 3) Clock input current (HIGH) Clock input current (LOW) Reset output voltage (HIGH) Symbol ICC VSL VSH VTH ITH ITL VOH1 VOH2 VOL1 VOL2 VOL3 VOL4 IOL1 IOL2 ICT1 ICT2 VCCL1 VCCL2 S1 B B B B B B B B B B B B C A B B B B S2 OFF OFF OFF OFF OFF OFF OFF ON ON ON OFF OFF ON OFF OFF OFF OFF ON S3 OFF OFF OFF OFF OFF OFF ON OFF ON ON OFF OFF OFF OFF OFF OFF ON OFF S4 B B B B B B B C B B C C B B B B B A S5 OFF ON ON OFF OFF OFF ON ON ON ON ON ON ON ON OFF ON ON ON S6 ON ON ON ON ON ON ON ON ON ON ON ON ON ON OFF OFF ON ON S7 ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON VCC 5.0 V 5.0 to 4.0 V 4.0 to 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 0 to 2.0 V 0 to 2.0 V VCLK 5.0 V 3.0 V 3.0 V 0 to 3.0 V 5.0 V 0V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V - - 0V 0V VCT 0V 3.0 V 3.0 V 1.0V 0V 0V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 1.0 V 1.0 V 0V 0V IRESET - - - - - - -5.0 A - 3.0 mA 10 mA - - - - - - - - IRESET - - - - - - - -5.0 A - - 0.5 mA 1.0 mA - - - - - - Read ICC VO1, CRT1 VO1, CRT1 ICLK ICLK ICLK VO1 VO2 VO1 VO1 VO2 VO2 IO1 IO2 ICT ICT VO1, VCC VO2, VCC Reset output voltage (LOW) Reset output sink current (Note (N t 4) CT charge current 1 CT charge current 2 Minimum power supply for RESET (Note 5) Minimum power supply for RESET (Note 6) NOTES: 1. Decrease VCC from 5.0 V to 4.0 V and note the VCC value when VO1 (observed on CRT1) transitions to an abrupt LOW state. 2. Increase VCC from 4.0 V to 5.0 V and note the VCC value when VO1 (observed on CRT1) transitions to an abrupt HIGH state. 3. Increase the Clock voltage (VCLK) from 0 V to 3.0 V and observe the value of VCLK when ICLK transitions to an abrupt increase. 4. Measured with VO0 = 1.0 V. 5. Increase VCC from 0 V to 2.0 V and note the VCC value when VO1 (observed on CRT1) transitions to an abrupt LOW state. The VO1 value will initially track the VCC voltage increase until the internal circuit bias becomes active, at which time the VO1 value will return to a LOW state. 6. Increase VCC from 0 V to 2.0 V and note the VCC value when VO2 (observed on CRT2) starts to track the VCC voltage. 2001 Aug 22 12 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 100 pF R 2.2 k VCC S1 8 CRT CRT1 CT 1 RESET 7 VS 6 RCT 5 VCC A B C CRT CRT4 RESET 2 CLK 3 GND 4 VCCA S2 0.1 F CRT CRT2 20pF CRT CRT3 R 10 k A B VCLK C VCLKA SL01285 Figure 24. Test Circuit 2 (AC parameters). Table 2. Switch and power supply settings, AC parameters Parameter VCC pulse width for detection (Note 1) Clock input pulse width (Note 2) Clock input cycle (Note 3) Symbol tP1 S1 C S2 C 5.0 V 4.0 V t1 VCCA VCC - 1.4 V 0V t2 VCLKA VCLK - CRT 1, 2, 3 t3 tCLKW A C - 5.0 V 1.4 V 0V t2 - t2 1, 2, 3 tCLK A C - 5.0 V 1.4 V 0V t2 t3 - 1, 2, 3 Watchdog monitoring time Watchdog reset time Power-on reset delay time RESET, RESET propagation delay time tWDM tWDR tPR tPD1 A A B to A C A A A B 5.0 V 4.0 V - - - 5.0 V 5.0 V 5.0 V - - - - - 5.0 V 5.0 V 5.0 V 0V 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 tPD2 C B 5.0 V 4.0 V - - 0V 2, 3 RESET, RESET rise time RESET, RESET fall time NOTES: 1. t1 = 8.0 s. 2. t2 = 3.0 s. 3. t3 = 20 s. tR1 tR2 tF1 tF2 A A A A A A A A - - - - 5.0 V 5.0 V 5.0 V 5.0 V - - - - 5.0 V 5.0 V 5.0 V 5.0 V 1 3 1 3 2001 Aug 22 13 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 PACKING METHOD The NE56605-42 is packed in reels, as shown in Figure 25. GUARD BAND TAPE REEL ASSEMBLY TAPE DETAIL COVER TAPE CARRIER TAPE BARCODE LABEL BOX SL01305 Figure 25. Tape and reel packing method 2001 Aug 22 14 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 SO8: plastic small outline package; 8 leads; body width 3.9 mm pin 1 index B2 1.73 0.068 4.95 4.80 0.189 0.195 0.51 0.33 0.013 0.020 4.95 4.80 1.27 0.38 0.050 0.015 0.076 0.003 SO8 2001 Aug 22 15 Philips Semiconductors Product data System reset with built-in watchdog timer NE56605-42 Data sheet status Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Date of release: 10-01 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 9397 750 08733 Philips Semiconductors 2001 Aug 22 16 |
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